The invention relates to level shifting circuitry and other circuitry that is particularly useful in converting high speed streams of serial data having TTL logic levels to parallel signals that are suitable for driving current switches of a high speed digital-to-analog converter; the invention also relates to level shifting circuits that achieve high speed conversion of signals having TTL logic levels to corresponding signals having ECL logic levels and are capable of driving high capacitance loads.
High speed, low cost 16 bit digital-to-analog converters (DACs) are now commercially available. Low cost 16 bit digital-to-analog converters would find wider application if they could be economically connected to receive continuous, high speed serial streams of data having common TTL logic levels. An example of a high speed, low cost 16 bit digital-to-analog converter is the device marketed by the assignee having the part number PCM54.
There are certain applications in which high fidelity audio information is converted into a continuous serial digital format that is stored on an appropriate media, for example, on devices commonly known as "compact audio disks". When the audio disks are "played" on a suitable audio player, the serial digital stream of data is reproduced and fed into a suitable digital-to-analog converter to recreate the original high fidelity audio signals. Although the above-mentioned high speed, low cost 16 bit DAC is available, it must receive the digital information in the form of 16 bit digital words that are applied to its 16 digital inputs. Designing of a low cost serial-to-parallel converter capable of continuously applying 16 bit digital words to the digital inputs or bit current switches of the 16 bit DAC from the continuous, uninterrupted stream of serial digital data has produced a substantial challenge because of the conflicting requirements of very high speed operation and a low cost implementation.
The difficulties encountered in making a low cost serial-to-parallel converter to be included on a single bipolar integrated circuit chip with a digital-to-analog converter lead to a need to significantly reduce the complexity of prior serial-to parallel converter circuits. The internal circuit structure of the type of DAC referred to requires three power supplies, +V.sub.CC, ground, and -V.sub.CC, and the system requires that the digital inputs be TTL levels between +V.sub.CC and ground, but the bit switching circuitry of the DAC requires digital signals between the ground and -V.sub.CC. This leads to the need to not only internally convert TTL input levels to ECL levels, but also leads to a need to have the internal ECL levels shifted between ground and -V.sub.CC, if high speed ECL technology is to be used in implementing the desired serial-to-parallel conversion. The problems of both obtaining signal level shifting and conversion of the TTL clock and data signal levels present especially difficult design challenges. Although a variety of prior techniques are known for converting TTL input signals to voltage levels suitable for other logic families, such as the ECL, NMOS, and CMOS technologies, such prior techniques are deemed to be inadequate for meeting the present objectives of providing a low cost, high speed implementation of the needed serial-to-parallel converter.